1. Field of the Invention
This invention relates to a new logic family style that can be created using any modern CMOS fabrication process and can be tuned to any desirable hardening level up to multiple node upset immunity.
2. Background of the Invention
The current state of knowledge is as follows. Design of electronics for radiation environments has been notoriously difficult. Problems arise from changes in circuit performance (leakage currents, transistor drive degradation) that can be caused by the total ionizing dose radiation over time. Certain structures are susceptible to latchup events that can cause a performance loss and even permanent damage to the circuit structures. The CMOS devices are also known to be sensitive to upsets caused by an energized particle passing through a circuit region, depositing enough charge to change the state of the circuit node.
There are many known techniques have proven effective for mitigation of latchup and TID issues through the use of layout techniques (referred to as hardened by design) and/or fabrication (hardened processing). As technology fabrication technologies advance further into the ultra-deep-submicron region, the many standard bulk foundries have shown to have greater immunity to TID and SEL without any modifications to their commercial process. Advances in the processing materials and the decrease in gate oxide thickness allow greater immunity to TID effects. Lower operating voltages and control of the well resistivity can lead to virtually eliminating SEL issues in modern designs. As these TID and SEL issues become less intrusive in the advanced CMOS technologies, the heavy-ion induced single-event upset (SEU) and single-event transient (SET) errors have become the dominant issue remaining for modern circuit designs.
The primary goal of moving to a new technology from an older technology node is to increase circuit performance and design density. Circuit performance increases are generally based on the reduction of capacitance from the smaller feature sizes. This reduction of capacitance also reduces the amount of charge needed to change the state of the circuit node, which means the circuit nodes are becoming much more susceptible to heavy-ion upsets. The improvement in circuit density is created by the ability of placing a greater number of smaller transistors in a smaller region than previously possible. This crowding also makes it much easier to upset multiple nodes simultaneously from a single ion strike. In the true space environment, the heavy ion particles will be impacting the circuit from all possible angles. It is possible that a single particle could pass through a device just below the surface of the active components and travel parallel with the design, depositing charge to all nodes along the trajectory of this particle. Unlike the decreasing TID and SEL phenomena, the advancement created in modern fabrication processes have shown more prevalent heavy-ion induced upsets, and known hardening techniques are becoming impractical for implementation (at best) or virtually ineffective at mitigating these errors.
Accordingly, there is a need for a new logic family style that can be created using any modern CMOS fabrication process and can be tuned to any desirable hardening level up to multiple node upset immunity.